This application claims the priority benefit of Taiwan application serial no. 89114706, filed Jul. 24, 2000.
1. Field of the Invention
This invention relates to a method of fabricating a semiconductor integrated circuit, and more particularly, to a method of reducing surface humps of a doped amorphous silicon layer.
2. Description of Related Prior Art
A capacitor is often used for storing signal in a Dynamic Random Access Memory (DRAM). The more charges a capacitor stores; the less noise (such as soft errors created xcex1 particles) and refresh frequency there are in data access.
How to obtain sufficient capacitance in a capacitor is therefore a very important issue for fabricating semiconductors with a line width of 0.25 xcexcm to 0.18 xcexcm or below. One of the popular solutions is to increase the surface area of a capacitor, for example, increases the ruggedness of the surface area of a bottom electrode of a capacitor using hemi-spherical grain (HSG).
A conventional HSG forming process comprises a step of depositing a doped amorphous silicon layer, followed by a step of seeding and annealing. An HSG layer is formed via a re-crystallization process on the surface of the doped amorphous silicon layer.
While forming HSG on the surface of a bottom electrode of a capacitor; first, a metal oxide semiconductor (MOS) is formed underlying a dielectric layer on a substrate. The dielectric layer is then patterned to form contact windows. A doped amorphous silicon layer is deposited in the contact windows and on the dielectric layer, followed by a patterning process to the doped amorphous silicon layer to form HSG on the surface of a bottom electrode, hence to complete the fabrication of a bottom electrode of a capacitor.
A conventional deposition process of a doped amorphous silicon layer is completed in a single deposition step with a deposition gas source of SiH4 or Si2H6, and a doping gas source of PH3. After deposition of the doped amorphous silicon layer in the contact windows and on the dielectric layer, humps appear at the central areas over the substrate. The number of humps is proportional to the thickness of the doped amorphous silicon layer; i.e., the thicker the doped amorphous silicon layer is, the more humps there are. These humps cause problems for subsequent processes of coating photoresist and photolithography. As a result, the yield of products is affected.
As an example, using SiH4 and PH3 as deposition and doping gas sources at a deposition temperature of 600 degree Celsius to form a doped amorphous silicon layer with a thickness of 3083 angstroms, the number of defects is 99. However, using Si2H6 and PH3 as deposition and doping gas sources at a deposition temperature of 570 degree Celsius to form a doped amorphous silicon layer with a thickness of 5894 angstroms, the number of defects is 29. If the deposition layer has a thickness of 8382 angstroms, under the same deposition conditions, the number of defects is between 89 to 179. The above data illustrates that the number of defect increases as the deposition thickness of the doped amorphous silicon layer increases. Normally, the number of defect greater than 75 is not acceptable.
This invention provides a method for reducing surface humps of a doped amorphous silicon layer.
The method provided by the invention uses three deposition steps to reduce the number of surface humps of a doped amorphous silicon layer.
Furthermore, the invention provides a method using an undoped amorphous silicon layer or a lightly doped amorphous silicon layer to reduce the number of surface humps of a doped amorphous silicon layer.
The invention provides a method for reducing the surface hump phenomena of a doped amorphous silicon layer. A dielectric layer is formed on a substrate comprising several devices. The dielectric layer is patterned to form openings for exposure of a part of an electrode surface of the devices. The method provided by this invention comprises a first deposition step of forming a conformal first amorphous silicon layer in the openings and on the dielectric layer. A second deposition step is performed to form a second amorphous silicon layer on the first amorphous silicon layer and filling the openings. A third deposition step is performed to form a third layer of amorphous silicon layer on the second amorphous silicon layer.
In the above method, preferably, the first and third amorphous silicon layers are doped, while the second amorphous silicon layer is either lightly doped or undoped.
The foregoing first deposition step uses, preferably, SiH4 and PH3 as the deposition and doping gas sources with flow rates between about 800 to about 1000 and about 70 to about 90 sccm (standard cubic centimeter per minute), respectively. The deposition temperature is preferably between about 590 to about 610 degree Celsius, while the pressure of deposition chamber is, preferably, between about 180 to about 220 Torr.
The second deposition step uses, preferably, SiH4 and PH3 as the deposition and doping gas sources with flow rates between about 800 to about 1000 and about 0 to about 35 sccm, respectively. The deposition temperature is preferably between about 590 to about 610 degree Celsius, while the pressure of deposition chamber is, preferably, between about 180 to about 220 Torr.
The third deposition step uses, preferably, Si2H6 and PH3 as the deposition gas and doping sources with flow rates between about 180 to about 220 and about 260 to about 320 sccm, respectively. The deposition temperature is preferably between about 560 to about 580 degree Celsius, while the pressure of deposition chamber is, preferably, between about 50 to about 70 Torr.
According to the above, this invention has at least the following advantages. Using an undoped amorphous silicon layer, or a lightly doped amorphous silicon layer in the second deposition step to solve surface hump problem at central areas of a wafer after deposition of a doped amorphous silicon layer. The invention also eliminates problem of misalignment in subsequent photolithography and etching process, hence significantly increases the yield of products.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.